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Implementation of Encryption Algorithms in VHDL Language
Kožený, Petr ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This thesis deals with design and implementation of AES and DES encryption architectures for embedded systems. Architectures are implemented in VHDL language and design for FPGA technology. The proposed implementations are mapped on the Xilinx Spartan 3 technology. Both architectures are applied in simple ECB (Electronic Codebook) scheme with cache memories. A maximum throughput of design DES architecture 370 Mbps is achived with clock frequency of 104 MHz. The throughput of AES architecture at the maximum clock frequency of 118 MHz is 228 Mbps. Compared to software implementations for embedded systems, we achieve significantly higher throughput for both architectures.
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Software for manual delineation of ECG signals
Jež, Radek ; Kozumplík, Jiří (referee) ; Vítek, Martin (advisor)
This thesis deals with evaluation EKG in terms of classification rhythm and analysis HRV. In theoretic part of work are described basics of heart physiology and its usual pathology, basics of electrocardiography, evaluation EKG and standard methods of HRV evaluation. In practical part are described algorithms used in created application. Mainly describes technique of rhythm evaluation, ectopic rhythms and delineation error elimination, data preparing for HRV evaluation, drift removal from DES and HRV evaluation methods. Created program was tested on CSE and MIT- BIH database records. For lack of suitable data and absence of tested data, it wasn’t possible to test all the classification rules of used algorithms. Tested part of program appears reliable and functional.
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Security of real time multimedia data transmission
Otoupalík, Petr ; Koutný, Martin (referee) ; Hošek, Jiří (advisor)
This thesis deals with technology and security of real-time multimedia data transmission. The possibilities of the security of a multimedia data transfer and the mechanisms defined for the security of the signaling protocols SIP and H.323 are described with the view of security. The possible attacks on the real-time transfers are also mentioned. The basic requirements on the safe and reliable data transfer are specified. The main part of this thesis is focused on the security analysis of the data transmission of the selected communication clients, which use different security methods. The last part of the thesis deals with realization of simple attacks on multimedia data transmission and also on the SIP protocol.
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Acceleration of Data Encryption Algorithms in FPGA
Gajdoš, Miroslav ; Kaštil, Jan (referee) ; Šimek, Václav (advisor)
This work deals with the possibility of acceleration algorithm using reconfigurable FPGA circuits and speed of implementation by examining the difference compared to software implementation. The work describes the basics of encryption and acceleration algorithms on the FPGA. It then addresses the process of design, implementation, simulation and synthesis of the resulting implementation. It made analysis of the achieved solution. The aim of the project was to create a functional solution of accelerated algorithm, thus enabling its use in the real application and, finally, establishment of czech written material on this issue.
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Side channels - preparation of lab task
Holemář, Jan ; Malina, Lukáš (referee) ; Martinásek, Zdeněk (advisor)
This thesis deals with side-channel cryptoanalysis. It is focused on power side-channel attack on cryptographic device. The smart card Gemalto .NET is used as the cryptographic device. This smart card performs encryption through algorithm RSA, DES, AES. The power consumption of the smart card was scanned by a Tektronix CT-6 current probe. Data obtained by measuring were processed on the computer with relevant software and provided important information about the encryption key that was used.
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Hardware Acceleration of Encryption Algorithms Using Xilinx Zynq Technology
Linner, Marek ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The main concern of this paper are two world standard encryption algorithms Data Encryption Standard DES (DES for short) and Advanced Encryption Standard (further mentioned as AES). For these two respective algorithms, three publicly available implementations are integrated into a benchmarking code in C programming language. The code has been executed, implementations measured with three different input block lengths and bitrate calculated for each implementation. The thesis also includes hardware implementation of both encryption algorithms DES and AES using VHDL language, simulation of the synthesised circuits and calculation of the hardware implementations' bitrate using Vivado simulator's timing reports. These measured bitrates are then compared with the bitrates of benchmarked software implementations. Paper includes all source codes of the benchmarking C program and VHDL implementation, along with program written in C# used to generate VHDL components and another C# program used for automated testing.
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Identification of Ink Cartridges of Industrial Printer
Galád, Dominik ; Sysel, Petr (referee) ; Číka, Petr (advisor)
This thesis deals with the identification of ink cartridges by the industrial printer TSjet. There are described the basic methods of identification of ink cartridges that are commonly used today. There is also described 1-Wire® bus and USART interface. In the second part the thesis deals with suitable security algorithms for data security stored on the identification chip. The practical part describes the design of the system for identification of the ink cartridge. The conclusion of the thesis summarizes the results of design testing in practice and the safety evaluation of the whole system.
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Implementation of Encryption Algorithms in VHDL Language
Fruněk, Lukáš ; Fukač, Tomáš (referee) ; Kořenek, Jan (advisor)
The thesis deals with the design and implementation of the encryption algorithms DES and AES, operating in the CTR mode. The designed modules are implemented in the VHDL language and are mapped in the FPGA Intel Arria 10 SX 480. Algorithms are optimized for maximum throughput using loop unrolling and inner pipelining. The encryption module for DES reaches throughput of 26.2 Gbit/s with the circuit operating 410 MHz, and the module for AES reaches throughput of 34.6 Gbit/s with the circuit operating at 271 MHz. The reached throughput is in the order of thousand times faster than of the same encryption algorithms implemented in software for built-in microprocessors.
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Cryptography and modern cryptographic algorithms
Orság, Dominik ; Dobrovský, Ladislav (referee) ; Nevoral, Tomáš (advisor)
The goal of this bachelor thesis is to provide a comprehensive overview of the historical development of cryptography as well as important cryptographic methods of today. The theoretical section begins with an exploration of fundamental concepts and the historical progression of cryptographic algorithms. This is followed by a descroption of modern symmetric and asymmetric algorithms. The greatest attention is paid to the RSA algorithm and its implementation in the Python language.
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